Shared memory architecture

Results: 104



#Item
91Concurrent computing / Rendezvous / Test-and-set / Interrupt / Linearizability / Sleep / Lock / Mutual exclusion / Spinlock / Concurrency control / Computer architecture / Computing

Process Sleep and Wakeup on a Shared-memory Multiprocessor Rob Pike Dave Presotto Ken Thompson Gerard Holzmann

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Source URL: plan9.bell-labs.com

Language: English - Date: 2007-04-15 17:41:14
92Concurrent computing / Computer architecture / Cache coherence / Transactional memory / Linearizability / Consistency model / Algorithm / Software bug / Sequential consistency / Computing / Transaction processing / Concurrency control

TESTING MEMORY CONSISTENCY OF SHARED-MEMORY MULTIPROCESSORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

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Source URL: xenon.stanford.edu

Language: English - Date: 2008-02-26 14:40:30
93Information / Michael Stonebraker / Stanley Zdonik / Database / Conference on Innovative Data Systems Research / SIGMOD / In-memory database / Shared nothing architecture / Database management systems / Data management / Data

Jennie Duggan (n´ ee Rogers) MIT CSAIL 32 Vassar Street, Room G904B Cambridge, MA 02139

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Source URL: people.csail.mit.edu

Language: English - Date: 2014-09-29 20:04:28
94Central processing unit / Microprocessors / Parallel computing / Instruction set architectures / CPU cache / X86 / Multithreading / Multi-core processor / Microarchitecture / Computer architecture / Computer hardware / Computing

1 Directoryless Shared Memory Architecture using Thread Migration and Remote Access Keun Sup Shim∗ , Mieszko Lis∗ , Omer Khan‡ and Srinivas Devadas∗ ∗ Massachusetts

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Source URL: people.csail.mit.edu

Language: English - Date: 2014-05-09 15:17:07
95Computer engineering / Cache / CPU cache / Computer memory / Microarchitecture / Out-of-order execution / Instruction-level parallelism / Pentium Pro / Parallel computing / Computer architecture / Computer hardware / Central processing unit

Appeared in the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October[removed]Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors Parthas

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Source URL: barroso.org

Language: English - Date: 2005-03-07 23:35:18
96Parallel computing / Concurrent computing / Distributed computing architecture / Shared memory / Ipcs / Memory segmentation / Shared / Muttahida Qaumi Movement / Computing / Memory management / Inter-process communication

InterProcess Communication Shared Memory Ken Gottry Jan-2002 IPCS

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Source URL: kgottryjoy.gottry.com

Language: English - Date: 2002-04-18 19:40:46
97Parallel computing / Unified Parallel C / Thread / Memory model / Universal Product Code / Lock / Parallel programming model / Barrier / Shared memory / Computing / Concurrent computing / Computer programming

Performance Monitoring and Evaluation of a UPC Implementation on a NUMA Architecture François Cantonnet, Yiyi Yao, Smita Annareddy, Ahmed S. Mohamed*, Tarek A. El-Ghazawi Department of Electrical and Computer Engineerin

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Source URL: www.gwu.edu

Language: English - Date: 2013-12-04 13:04:25
98Graphics hardware / Silicon Graphics / Video card / SGI O2 / Bus / Dynamic random-access memory / Computer workstations / Shared graphics memory / Computer hardware / Motherboard / Computer memory

UNIFIED MEMORY ARCHITECTURE Summary

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Source URL: www.futuretech.blinkenlights.nl

Language: English - Date: 2003-03-12 08:39:22
99Computer hardware / Non-Uniform Memory Access / Uniform memory access / Shared memory architecture / Memory architecture / SMP - Symmetric Multiprocessor System / Computer architecture / Intel QuickPath Interconnect / Microarchitecture / Computing / Parallel computing / Computer memory

Non-Uniform Memory Access (NUMA) Nakul Manchanda and Karan Anand New York University

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Source URL: cs.nyu.edu

Language: English - Date: 2010-05-04 11:32:53
100Cache coherency / Distributed computing architecture / Cache coherence / Cache / Shared memory / Multi-core processor / Coherence / MOESI protocol / Consistency model / Concurrent computing / Computing / Parallel computing

CACHE COHERENCE TECHNIQUES FOR MULTICORE PROCESSORS by

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Source URL: www8.cs.umu.se

Language: English - Date: 2009-02-13 04:23:23
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